Changes between Version 6 and Version 10 of Ticket #364
- Timestamp:
- 02/28/09 00:53:14 (13 years ago)
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Ticket #364 – description
v6 v10 1 1 Sparc 64bit with strict ptr_alignment=8 breaks when reading frozen pmc's because of misalignment. 2 2 3 Any 64bit big-endian cpu with strict alignment is broken without '''-xmemalign= 2i''' (the immediate workaround)3 Any 64bit big-endian cpu with strict alignment is broken without '''-xmemalign=4s''' (the immediate workaround) 4 4 The default for all v9 architectures is '''-xmemalign=8s'''. 5 5 6 6 However, our goal should be to allow fast aligned code and not to skip this with a compiler relaxement. 7 8 {{{9 * First we should align to the foreign pbc ptrsize, not to the native ptrsize.10 * /sizeof (opcode_t) => /header->wordsize11 */12 #define ROUND_16(val) (((val) & 0xf) ? 16 - ((val) & 0xf) : 0)13 #define ALIGN_16(st, cursor) \14 (cursor) += ROUND_16((const char *)(cursor) - (const char *)(st))/sizeof (opcode_t)15 }}}16 17 This requires a check for all ptr alignment code (no macros used, bad) and to find the source of the problem, most likely a string.18 7 19 8 {{{ … … 43 32 Sparc cc manpage:[[BR]] 44 33 -xmemalign[=<a><b>] Controls memory alignment, <a>={1|2|4|8|16}, b={f|i|s}.[[BR]] 45 Accepted values for b are: i Interpret access and continue execution. s Raise signal SIGBUS. f For variants of -xarch=v9 only. [reduced i] 34 Accepted values for b are:[[BR]] 35 i Interpret access and continue execution.[[BR]] 36 s Raise signal SIGBUS. [[BR]] 37 f For variants of -xarch=v9 only. [reduced i] [[BR]] 46 38 47 39 Thanks to Rolf Grossmann for coming up with all this info and debugging, and to Andy Dougherty for correcting my wrong first analysis. 40 41 The fix for 1.0 will be a hints file update to add -xmemalign=4s to cc_flags, the goal for 2.6 will be a --64bitcompat argument to parrot to create 8-byte aligned values on 32-bit, not 4-byte as now.